Oversampled sigma-delta digital-to-analog (D/A) and analog-to-digital (A/D) converters use interpolation and decimation filters, respectively. Such filters typically require a high frequency clock signal that is a binary multiple of either an input sample rate or an output sample rate. That is, the interpolation filter in the D/A converter requires a high frequency clock signal that is a simple binary multiple of the input sample rate, whereas the A/D converter, using a decimation filter, usually requires a high frequency clock signal that is a simple binary multiple of the output sample rate.
FIG. 1 shows a conventional sigma-delta D/A converter 30. Digital input data 32, a frame clock 34, and a high-speed master clock 36 are inputs to the converter. The high speed master clock is a simple binary multiple of the frame clock, and is typically 64, 128, or 256 times higher than the input rate. An interpolation filter 38 takes the digital input data 32 in at the frame clock rate, i.e., the input rate (Fs.sub.-- in), and produces an interpolated output 40 at the rate of the high-speed master clock. The clocks to drive the interpolation filter and other parts of the D/A converter 30 are provided by a clock generator 50 which receives the frame clock and the master clock and generally divides them appropriately. The interpolated output 40 is then fed to a noise shaping circuit 42 that provides an output 44 with a reduced number of bits, to a small number often as low as 1 (a single bit). A D/A converter 46 provides an analog output 48 according to the output 44 of the noise shaper 42.
In systems where a variety of input sample rates must be accommodated, generating the required high frequency master clock that is, for example, 64 times the input sample rate can be difficult. Frequently, an analog phase-locked loop (PLL) is required to generate this clock. Thus, digital integrated circuits designed to perform such D/A conversion have an input for receiving the high frequency signal which is presumed to be phase-locked to the input data, and it is assumed that the user of such a circuit will use an analog PLL to generate the master clock. Thus, an asynchronous master clock cannot be used.
Digital PLLs are generally not used because the use of a digital PLL to generate the high frequency master clock based on the input clock (Fs.sub.-- in) normally leads to serious performance degradation due to the fact that the clock signal the digital PLL produces must switch on a system master clock edge which is asynchronous relative to the input clock. Since the system master clock rate has no relationship with the input sample rate, there will be a variable number of system master clock pulses for each 64*Fs.sub.-- in clock pulse. For example, with a system master clock frequency of 7 MHZ and a high frequency master clock frequency of 64*FS.sub.-- in (approximately 3 MHZ), there will be on average 7/3 system master clock pulses for each cycle of the 3 MHZ signal. Since the 64*FS.sub.-- in clock signal is generated by a digital PLL that is clocked with the system master clock, some cycles of the 64*FS.sub.-- in clock signal will last for two system master clock cycles, and some will last for three system master clock cycles, in such a way as to make the average equal to 7/3. This translates to a large amount of jitter on the output of the digital PLL, which would cause distortion and noise to occur in the resulting analog signal at the output of the D/A converter 46.
It is preferable to use a digital PLL to provide a single digital integrated circuit which accommodates a number of input sample rates but which eliminates the requirement of an analog PLL and allows a user to provide only an asynchronous master clock instead of a master clock phase-locked to the input rate. Such a system has been provided by Analog Devices, Inc., in a product called the AD1843. While this product has distinct advantages, a complex noise shaping scheme is used to overcome the problems caused by using a digital PLL.